Opcode

Opcodes (short for Operation Codes) are processor instructions used in machine language. The 6510 CPU offers 151 official opcodes, plus 105 illegal (unofficial) opcodes, totaling 256 opcodes.

Legal Opcodes

Examples:

• $C8 (11001000) is the opcode for the mnemonic INY.
• $EA (11101010) is the opcode for the mnemonic NOP.

Illegal Opcodes

Illegal opcodes are undocumented commands that exist as a side-effect of the hardwired circuit design and were called "illegal" because they are not guaranteed to work reliably.

Opcode matrix for MOS 6510

Illegal Opcodes are coloured red.

x0

x1

x2

x3

x4

x5

x6

x7

x8

x9

xA

xB

xC

xD

xE

xF

0x

BRK imp

ORA inx

JAM

SLO inx

NOP zp

ORA zp

ASL zp

SLO zp

PHP imp

ORA imm

ASL akk

ANC imm

NOP abs

ORA abs

ASL abs

SLO abs

1x

BPL rel

ORA iny

JAM

SLO iny

NOP zpx

ORA zpx

ASL zpx

SLO zpy

CLC imp

ORA aby

NOP imp

SLO aby

NOP abx

ORA abx

ASL abx

SLO abx

2x

JSR abs

AND inx

JAM

RLA inx

BIT zp

AND zp

ROL zp

RLA zp

PLP imp

AND imm

ROL akk

ANC imm

BIT abs

AND abs

ROL abs

RLA abs

3x

BMI rel

AND iny

JAM

RLA iny

NOP zpx

AND zpx

ROL zpx

RLA zpy

SEC imp

AND aby

NOP imp

RLA aby

NOP abx

AND abx

ROL abx

RLA abx

4x

RTI imp

EOR inx

JAM

SRE inx

NOP zp

EOR zp

LSR zp

SRE zp

PHA imp

EOR imm

LSR akk

ALR imm

JMP abs

EOR abs

LSR abs

SRE abs

5x

BVC rel

EOR iny

JAM

SRE iny

NOP zpx

EOR zpx

LSR zpx

SRE zpx

CLI imp

EOR aby

NOP imp

SRE aby

NOP abx

EOR abx

LSR abx

SRE abx

6x

RTS imp

ADC inx

JAM

RRA inx

NOP zp

ADC zp

ROR zp

RRA zp

PLA imp

ADC imm

ROR akk

ARR imm

JMP ind

ADC abs

ROR abs

RRA abs

7x

BVS rel

ADC iny

JAM

RRA iny

NOP zpx

ADC zpx

ROR zpx

RRA zpx

SEI imp

ADC aby

NOP imp

RRA aby

NOP abx

ADC abx

ROR abx

RRA abx

8x

NOP imm

STA inx

NOP imm

SAX inx

STY zp

STA zp

STX zp

SAX zp

DEY imp

NOP imm

TXA imp

ANE imm

STY abs

STA abs

STX abs

SAX abs

9x

BCC rel

STA iny

JAM

SHA iny

STY zpx

STA zpx

STX zpy

SAX zpy

TYA imp

STA aby

TXS imp

TAS aby

SHY abx

STA abx

SHX aby

SHA aby

Ax

LDY imm

LDA inx

LDX imm

LAX inx

LDY zp

LDA zp

LDX zp

LAX zp

TAY imp

LDA imm

TAX imp

LAX imm

LDY abs

LDA abs

LDX abs

LAX abs

Bx

BCS rel

LDA iny

JAM

LAX iny

LDY zpx

LDA zpx

LDX zpy

LAX zpy

CLV imp

LDA aby

TSX imp

LAS aby

LDY abx

LDA abx

LDX aby

LAX aby

Cx

CPY imm

CMP inx

NOP imm

DCP inx

CPY zp

CMP zp

DEC zp

DCP zp

INY imp

CMP imm

DEX imp

SBX imm

CPY abs

CMP abs

DEC abs

DCP abs

Dx

BNE rel

CMP iny

JAM

DCP iny

NOP zpx

CMP zpx

DEC zpx

DCP zpx

CLD imp

CMP aby

NOP imp

DCP aby

NOP abx

CMP abx

DEC abx

DCP abx

Ex

CPX imm

SBC inx

NOP imm

ISC inx

CPX zp

SBC zp

INC zp

ISC zp

INX imp

SBC imm

NOP

SBC imm

CPX abs

SBC abs

INC abs

ISC abs

Fx

BEQ rel

SBC iny

JAM

ISC iny

NOP zpx

SBC zpx

INC zpx

ISC zpx

SED imp

SBC aby

NOP imp

ISC aby

NOP abx

SBC abx

INC abx

ISC abx

Arrangement

The microcode of the 6502 is compressed into a 130-entry decode ROM. Instead of 256 entries telling how to process each separate opcode, it's encoded as combinational logic post-processing the output of a "sparse" ROM that acts in some ways like a programmable logic array (PLA). Each entry in the ROM means "if these bits are on, and these bits are off, do things on these six cycles.

Many instructions activate multiple lines of the decode ROM at once. Often this is on purpose, such as one line for the addressing mode and one for the opcode part. But many of the unofficial opcodes simultaneously trigger parts of the ROM that were intended for completely unrelated instructions.

Perhaps the pattern is easier to see by shuffling the 6502's opcode matrix. This table lists all 6502 opcodes, 32 columns per row. The columns are colored by bits 1 and 0: 00 red, 01 green, 10 blue, and 11 gray.

Key: a is a 16-bit absolute address, and d is an 8-bit zero page address. Entries in bold represent unofficial opcodes.

	+00	+04	+08	+0C	+10	+14	+18	+1C	+01	+05	+09	+0D	+11	+15	+19	+1D	+02	+06	+0A	+0E	+12	+16	+1A	+1E	+03	+07	+0B	+0F	+13	+17	+1B	+1F
00	BRK	NOP d	PHP	NOP a	BPL *+d	NOP d,x	CLC	NOP a,x	ORA (d,x)	ORA d	ORA #i	ORA a	ORA (d),y	ORA d,x	ORA a,y	ORA a,x	JAM	ASL d	ASL	ASL a	JAM	ASL d,x	NOP	ASL a,x	SLO (d,x)	SLO d	ANC #i	SLO a	SLO (d),y	SLO d,x	SLO a,y	SLO a,x
20	JSR a	BIT d	PLP	BIT a	BMI *+d	NOP d,x	SEC	NOP a,x	AND (d,x)	AND d	AND #i	AND a	AND (d),y	AND d,x	AND a,y	AND a,x	JAM	ROL d	ROL	ROL a	JAM	ROL d,x	NOP	ROL a,x	RLA (d,x)	RLA d	ANC #i	RLA a	RLA (d),y	RLA d,x	RLA a,y	RLA a,x
40	RTI	NOP d	PHA	JMP a	BVC *+d	NOP d,x	CLI	NOP a,x	EOR (d,x)	EOR d	EOR #i	EOR a	EOR (d),y	EOR d,x	EOR a,y	EOR a,x	JAM	LSR d	LSR	LSR a	JAM	LSR d,x	NOP	LSR a,x	SRE (d,x)	SRE d	ALR #i	SRE a	SRE (d),y	SRE d,x	SRE a,y	SRE a,x
60	RTS	NOP d	PLA	JMP (a)	BVS *+d	NOP d,x	SEI	NOP a,x	ADC (d,x)	ADC d	ADC #i	ADC a	ADC (d),y	ADC d,x	ADC a,y	ADC a,x	JAM	ROR d	ROR	ROR a	JAM	ROR d,x	NOP	ROR a,x	RRA (d,x)	RRA d	ARR #i	RRA a	RRA (d),y	RRA d,x	RRA a,y	RRA a,x
80	NOP #i	STY d	DEY	STY a	BCC *+d	STY d,x	TYA	SHY a,x	STA (d,x)	STA d	NOP #i	STA a	STA (d),y	STA d,x	STA a,y	STA a,x	NOP #i	STX d	TXA	STX a	JAM	STX d,y	TXS	SHX a,y	SAX (d,x)	SAX d	ANE #i	SAX a	SHA (d),y	SAX d,y	TAS a,y	SHA a,y
A0	LDY #i	LDY d	TAY	LDY a	BCS *+d	LDY d,x	CLV	LDY a,x	LDA (d,x)	LDA d	LDA #i	LDA a	LDA (d),y	LDA d,x	LDA a,y	LDA a,x	LDX #i	LDX d	TAX	LDX a	JAM	LDX d,y	TSX	LDX a,y	LAX (d,x)	LAX d	LAX #i	LAX a	LAX (d),y	LAX d,y	LAS a,y	LAX a,y
C0	CPY #i	CPY d	INY	CPY a	BNE *+d	NOP d,x	CLD	NOP a,x	CMP (d,x)	CMP d	CMP #i	CMP a	CMP (d),y	CMP d,x	CMP a,y	CMP a,x	NOP #i	DEC d	DEX	DEC a	JAM	DEC d,x	NOP	DEC a,x	DCP (d,x)	DCP d	SBX #i	DCP a	DCP (d),y	DCP d,x	DCP a,y	DCP a,x
E0	CPX #i	CPX d	INX	CPX a	BEQ *+d	NOP d,x	SED	NOP a,x	SBC (d,x)	SBC d	SBC #i	SBC a	SBC (d),y	SBC d,x	SBC a,y	SBC a,x	NOP #i	INC d	NOP	INC a	JAM	INC d,x	NOP	INC a,x	ISC (d,x)	ISC d	SBC #i	ISC a	ISC (d),y	ISC d,x	ISC a,y	ISC a,x

Thus the 00 (red) block is mostly control instructions, 01 (green) is ALU operations, and 10 (blue) is read-modify-write (RMW) operations and data movement instructions involving X. The RMW instructions (all but row 80 and A0) in columns +06, +0E, +16, and +1E have the same addressing modes as the corresponding ALU operations.

The 11 (gray) block is unofficial opcodes combining the operations of instructions from the ALU and RMW blocks. all of them having the same addressing mode as the corresponding ALU opcode. The RMW+ALU instructions that affect memory are easiest to understand because their RMW part completes during the opcode and the ALU part completes during the next opcode's fetch. Column +0B, on the other hand, has no extra cycles; everything completes during the next opcode's fetch. This causes instructions to have strange mixing properties. Some even differ based on analog effects.

Links

• 6502/6510/8500/8502 opcodes (including illegal) at oxyron.de
• NMOS 6510 Unintended Opcodes (No More Secrets)