Hardware internals of the C64

C64 Mainboard KU-14194HB

This article describes the Hardware internals of the C64. Basic knowledge of computer hardware and circuit design is assumed. A general explanation of the C64's capabilities can be found in the overview article on the C64.

Simplified Block Diagram

                  ┌──────┐ ┌──────┐ ┌──────┐   ┌────────┐
                  │ BASIC│ │KERNAL│ │  CHAR│   │    8x8k│
                  │   ROM│ │   ROM│ │   ROM│   │     RAM│
                  └┬─┬─┬─┘ └┬─┬─┬─┘ └┬─┬─┬─┘   └┬─┬───┬─┘
                   │ │ │    │ │ │    │ │ │      │ │   │
   ┌─────┐enable   │ │ │    │ │ │    │ │ │      │ │   │
   │ PLA ├>───────┬┴─┼─┼───┬┴─┼─┼───┬┴─┼─┼─────┬┴─┼───┼─────┐
   └──┬──┘        │  │ │   │  │ │   │  │ │     │  │   │     │
      │           │  │ │   │  │ │   │  │ │     │  │8  │8    │
 ┌────┴──┐adr16   │  │ │   │  │ │   │  │ │     │ ┌┴┐  │     │
 │       ├<>──────┼─┬┴─┼───┼─┬┴─┼───┼─┬┴─┼─────┼─┤A├──┼───┐ │
 │  CPU  │data8   │ │  │   │ │  │   │ │  │     │ └┬┘ ┌┴┐ ┌┴─┴───┐
 │       ├<>──────┼─┼─┬┴───┼─┼─┬┴───┼─┼─┬┴─────┼──┼──┤D├─┤ColMem│
 └────┬──┘        │ │ │    │ │ │    │ │ │      │  ^  └┬┘4└┬─────┘
      │           │ │ │    ^ │ │    │ │ │      ^  v   │   │
      │          ┌┴─┴─┴─┐ ┌┴─┴─┴─┐ ┌┴─┴─┴┐    ┌┴──┴───┴───┴┐
      │          │ CIA1 │ │ CIA2 │ │ SID │    │   VIC-II   │
      │          └┬┬───┬┘ └─┬───┬┘ └─────┘    └────────────┘
      │  ┌────────┘├─┬─┤    │   │
     ┌┴──┴─┐     ┌─┴┐│┌┴─┐ ┌┴┐ ┌┴─┐
      Datas      Joy1│Joy2 Ser User
                    ┌┴┐                               connected ┴
                    Key                           no connection ┼

Notes

The chip designations (Uxx, etc.) and other explanations refer to the original C64 ("breadbox"). The schema of the Mainboard in later C64 variants differs slightly from this.

Detailed Circuit Diagram

• C64 schematics, page 1 (CPU, CIAs, Clock generation, Power supply, Ports excluding Expansion Port)
• C64 schematics, page 2 (RAM, color RAM, ROMs, PLA, VIC-II, SID, expansion port, audio/video circuity, including additional explanations)
• C64 schematics (both pages as PDF, without further explanations on page 2)

Interaction/PLA

• Most chips are directly connected to the 16-bit address bus and 8-bit data bus of the MOS 6510.
• Depending on the memory configuration and the addressed location, the PLA (U17) activates different chips.
• When addressing the I/O range, the demultiplexer U15 decides, in addition to the PLA, which chip will be activated.

Main Memory

• The dynamic 64k RAM is arranged in 8 chips of 65536 bits each; each chip is responsible for one bit of all memory bytes (U12 provides the most significant bit of each byte, etc.).
• The RAM has 8 address lines, which are connected in parallel to each chip. The addressing is multiplexed (CAS/RAS).
  • The CPU address bus (16 bits) is connected via U13/U25.
  • The VIC directly accesses the 8 multiplexed address lines of the RAM.

VIC Interface

• The VIC holds a special position because it needs to perform memory refresh and access memory during badlines. Therefore, its interface to the buses and the dedicated bus between Color RAM and VIC is somewhat more complex.
• The VIC takes control of the address buses when AEC (Address Enable Control) is low. This normally occurs on every clock cycle when Φ0=0, meaning the VIC and the CPU alternate accessing the RAM.
• With BA (Bus Available) low, the VIC can halt the CPU and access the RAM exclusively for longer periods. This typically happens every 8 scanlines during the Badline, to fetch Video Matrix Pointer, and also during non-badlines to fetch sprite data if sprites are enabled.
  • The 6510 cannot be halted during write states, which is why the VIC waits for three clock cycles after pulling BA low before also pulling AEC low at Φ0=1.
• The VIC's interface is not trivial; the chips U13, U14, U25, and U26 manage switching the address lines ("A" in the block diagram above) between VIC and CPU. U16 can connect the Color RAM to the data bus ("D" in the diagram).
  • The VIC has a 14-bit address bus (16k address space, hence the two extra bits via CIA2, allowing the bank for screen memory to be selected). The RAM refresh is done only via the 8 multiplexed address lines, so all 64kB of RAM can be refreshed without additional tricks.
  • The VIC's data bus is 12 bits wide (8 bits on the CPU data bus, 4 bits directly on the static Color RAM).
  • U14 is used to couple the two bank bits from the CIA into the VIC address bus or bypass them during RAM refresh.
  • U26 allows addressing the Char-ROM and Color-RAM via the VIC.
  • On AEC=0, U13 and U25 disconnect the CPU address bus from the RAM.
  • VIC access to the main memory is multiplexed via the 8 address lines to the RAM.
  • VIC access to Char-ROM, Color-RAM, and Cartridge-HIROM (in Ultimax mode) happens normally without multiplexing and through the CPU address bus, which is temporarily controlled by the VIC.
  • On AEC=0, only A0-A11 are controlled by the VIC (A8-A11 directly, A0-A7 via U26). A12-A15 are pulled high by the pull-ups in RP4. This means that during AEC=0, only addresses $F000-$FFFF are visible on the normal address bus. The Char-ROM can be made visible to the VIC only because the PLA inspects the VA lines at AEC=0 instead of the normal address bus.
  • In Ultimax mode, during AEC=0, either RAM or HIROM is always visible to the VIC.
  • Addressing (reading/writing) of the VIC's registers is done via the lower six address lines of the VIC, which are bidirectional and are written to an internal latch on RAS=0 and AEC=1.

Clock

• The Pixel Clock (~8 MHz Dot Clock) is generated by the circuit behind Y1.
• Φ0 (~1 MHz) is an output signal from the VIC, where the pixel clock divided by 8 is present. Φ0 is at least one gate delay relative to the pixel clock, has a 1:1 high/low ratio, and likely changes on the rising edge of the pixel clock.
• Φ2 is the delayed Φ0 by 30-40ns (temperature dependent) through the 6510. Φ2 is the main system clock. Sources: Gideon Zweijtzer in the CBM-Hackers List, Skoe's contribution on Thread: "Hardware layout of the C64" on c64-wiki.de on Forum64.de .
  • During Φ2=0, the VIC accesses the system, during Φ2=1 (mostly) the CPU.
  • The 6510 reads on the falling edge of Φ0. Source.
  • From the perspective of the 6510, these shifted clock signals are necessary because the 6510 is built with Dynamic Logic and with this technique, consecutive latches cannot be toggled simultaneously due to potential race conditions. Source.
  • At the high edge of Φ2, the data and address bus and R/W are not yet stable. The VIC releases AEC so late that the 6510 can activate its outputs only very late. Sources: Skoe's contribution on Thread: C128 Expansion Port Timing on Forum64.de , Post in comp.sys.cbm.
  • Caution: For example, in the 6510 datasheet, Φ0 does not appear, instead, Φ1 as an input clock is mentioned. This is probably historically driven: In the 6502 Φ0 was the input signal, at output Φ1 the Φ0 was slightly delayed and inverted, and output Φ2 was the "opposite clock" to Φ1 (short high when Φ1 is low). In the 6510 there is only one clock output. Details on the 6502.
• The TOD timers of the CIAs are clocked separately via U27 from the network clock (9V) (except SX64).

External Links

• C64 Schematics on zimmers.net

References

Hardware internals of the C64 · Hardware portal
Components of the C64: CPU · VIC · SID · CIA · PLA · RAM · ROM · Color RAM

Interfaces of the C64: Control Port · Expansion Port · Userport · Cassette Port · Power Supply Connector · A/V Jack · RF Jack · Serial Port