Expansion Port
The Expansion Port or Memory Expansion Port on older models, also called Module or Cartridge Port. This port is a rectangular opening at the back of the C64 case and is intended for expansions of the system. Basically it has similar function to ISA or PCI ports in a PC. Since many important signals of the C64 are led to the connector, this results in a wide range of applications. From just connecting a simple reset button, a modem or an EPROM programming device or maybe a SuperCPU there are almost all imaginable expansions possible. The expansion port is mainly used for plugging in cartridges which are usually utility cartridges such as Action Replay 6, The Final Cartridge 3 etc. but also games, other software and RAMexpansion.
Contrary to the user port there are no freely programmable lines on the expansion port, i.e. expansion port modules need to "listen" permanently to the data and address bus of the CPU MOS 6510 and affect the system with a conform timing. Therefore the expansion port is not as suitable for simple projects. On the positive side the connector can be made directly on the PCB, no unusual connector is needed.
Pin assignment[edit | edit source]
The expansion port is a 2-row EDGE connector with 44 contacts in total. The pitch of the contacts is 2.54 mm (0.1 inch).
| Pin | Signal | Direction (From C64) | Meaning | Remark |
|---|---|---|---|---|
| 1 | GND | PWR | Ground | Potential is 0V on ground, signal levels are measured relative this, can also be called "common ground". |
| 2 | +5V DC | PWR |
Supply voltage +5V DC |
The maximum load for extensions is 450mA. |
| 3 | ||||
| 4 | _IRQ | In/Out | Interrupt Request | see IRQ . As an output, reflects the status of the IRQ line |
| 5 | R/_W | In/Out | Read or _Write signal | High-level during read cycle, Low-level during write cycle |
| 6 | DOT Clk | Out | Dot clock frequency | 7.881984 MHz for PAL-systems ; 8.181816 MHz for NTSC-systems |
| 7 | _IO1 | Out | Input/Output area 1 indicator | Signal is low if address bus is within $DE00-$DEFF. |
| 8 | _GAME | In | Game configuration | Used for memory re-configuration; see PLA (C64-Chip) |
| 9 | _EXROM | In | External ROM | Similar to _GAME. During low the internal RAM in the range of $8000-$9FFF will be switched off and _ROML will be set low, if one of these addresses occur. |
| 10 | _IO2 | Out | Input/Output area 2 indicator | Signal is low if address bus is within $DF00-$DFFF. |
| 11 | _ROML | Out | ROM Low | Low signal if the address range is $8000-$9FFF is switched off with _EXROM and one of these addresses occur on the bus. |
| 12 | BA | Out | Bus Available | Signal from the video controller, which indicates if the bus is available during high phase of PHI2. BA=0 means VIC needs the bus during both phases of PHI2 and no other unit can use it. |
| 13 | _DMA | In | Direct Memory Access | if _DMA=Low the CPU can be requested to release the bus. It will stop after the next read cycle and all bus lines will go to high resistance state. So other units can use the computer hardware. At _DMA=High the CPU continues to work. |
| 14 | D7 | In/Out | Data line 7 | Bit 7 of data bus, value=128 |
| 15 | D6 | In/Out | Data line 6 | Bit 6 of data bus, value=64 |
| 16 | D5 | In/Out | Data line 5 | Bit 5 of data bus, value=32 |
| 17 | D4 | In/Out | Data line 4 | Bit 4 of data bus, value=16 |
| 18 | D3 | In/Out | Data line 3 | Bit 3 of data bus, value=8 |
| 19 | D2 | In/Out | Data line 2 | Bit 2 of data bus, value=4 |
| 20 | D1 | In/Out | Data line 1 | Bit 1 of data bus, value=2 |
| 21 | D0 | In/Out | Data line 0 | Bit 0 of data bus, value=1 |
| 22 | GND | PWR |
Ground |
(See above) |
| A | ||||
| B | _ROMH | Out | ROM High | Depending on the status of _GAME and _EXROM this line gets low during access to the address space between $A000-$BFFF respectively $E000-$FFFF. Condition: the internal ram area is faded out. |
| C | _RESET | In | Reset | If this line is pulled to low, all chips will be re-initialized. The program counter of the CPU will be loaded with the reset vector $FFFC and $FFFD (normally $FCE2). |
| D | _NMI | In | Non Maskable Interrupt | see NMI |
| E | PHI2 | Out | Phase 2 clock | System clock (0.98524861 MHz for PAL, 1.02272714 MHz for NTSC) |
| F | A15 | In/Out | Address line 15 | Bit 15 of address bus value=32768 |
| H | A14 | In/Out | Address line 14 | Bit 14 of address bus value=16384 |
| J | A13 | In/Out | Address line 13 | Bit 13 of address bus value=8192 |
| K | A12 | In/Out | Address line 12 | Bit 12 of address bus value=4096 |
| L | A11 | In/Out | Address line 11 | Bit 11 of address bus value=2048 |
| M | A10 | In/Out | Address line 10 | Bit 10 of address bus value=1024 |
| N | A9 | In/Out | Address line 9 | Bit 9 of address bus value=512 |
| P | A8 | In/Out | Address line 8 | Bit 8 of address bus value=256 |
| R | A7 | In/Out | Address line 7 | Bit 7 of address bus value=128 |
| S | A6 | In/Out | Address line 6 | Bit 6 of address bus value=64 |
| T | A5 | In/Out | Address line 5 | Bit 5 of address bus value=32 |
| U | A4 | In/Out | Address line 4 | Bit 4 of address bus value=16 |
| V | A3 | In/Out | Address line 3 | Bit 3 of address bus value=8 |
| W | A2 | In/Out | Address line 2 | Bit 2 of address bus value=4 |
| X | A1 | In/Out | Address line 1 | Bit 1 of address bus value=2 |
| Y | A0 | In/Out | Address line 0 | Bit 0 of address bus value=1 |
| Z | GND | PWR | Ground | (See above) |
