Bank Switching
Bank Switching is a technique which configures the memory accessible by the CPU at any given time.
As the MOS 6510 CPU can only access 216 = 65536 memory locations ($0000-$FFFF), banks of memory can be switched (which exposes or hides them from the CPU) in order to provide a greater overall capacity. In its original state the C64 contains 64 kBytes of RAM, 20 kBytes of ROM, and 512 bytes of Color RAM. Through the expansion port, extensions such as additional ROM and/or RAM can be added. Bank switching allows the CPU to access all of this memory (albeit non-contiguously) to execute a program, and is a common technique in 8-bit microcomputer systems. Unlike memory management by paging, data is not exchanged with a storage device but is loaded into memory and remains inaccessible to the CPU until bank switching is initiated.
Caution[edit | edit source]
Caution should be taken when bank switching away from the default configuration. Because the standard interrupt handling routines in ROM access the I/O hardware (for example in order to scan the keyboard), normal interrupt operations should be disabled when the I/O hardware is banked out (not accessible by the CPU). Likewise care should be taken to avoid the CPU trying to execute code expected from ROM, when that ROM is banked out.
Control bits[edit | edit source]
In order to achieve bank switching, the CPU needs access to a latch. For the C64, the Programmable Logic Array (PLA) acts as a latch which enables memory configurations by setting or clearing latch bits. The PLA is connected to the CPU control lines and the expansion port which, together, dictate which areas of memory are banked.
CPU Control Lines[edit | edit source]
The three least significant bits in the port register (address 1) correspond to the three control lines in the port used for bank switching. To use these control lines, they must be configured as outputs, i.e. the same three least significant bits in the port's directional data register (at address 0) must be set to 1. This is the default upon power-up, but a programmer may want to make certain of this before bank switching. The control lines, in general, perform the function given in their descriptions. However, a combination of control lines are occasionally used to set a particular memory configuration.
- LORAM (bit 0, weight 1) is a control line which banks the 8 kByte BASIC ROM in or out of the CPU address space. Normally, this line is logically high (set to 1) for BASIC operation. If this line is logically low (cleared to 0), the BASIC ROM will typically disappear from the memory map and be replaced by 8 kBytes of RAM from $A000-$BFFF. Some exceptions to this rule exist; see the table below for a full overview.
- HIRAM (bit 1, weight 2) is a control line which banks the 8 kByte KERNAL ROM in or out of the CPU address space. Normally, this line is logically high (set to 1) for KERNAL ROM operation. If this line is logically low (cleared to 0), the KERNAL ROM will typically disappear from the memory map and be replaced by 8 kBytes of RAM from $E000-$FFFF. Some exceptions to this rule exist; see the table below for a full overview.
- CHAREN (bit 2, weight 4) is a control line which banks the 4 kByte character generator ROM in or out of the CPU address space. From the CPU point of view, the character generator ROM occupies the same address space as the I/O devices ($D000-$DFFF). When the CHAREN line is set to 1 (as is normal), the I/O devices appear in the CPU address space, and the character generator ROM is not accessible. When the CHAREN bit is cleared to 0, the character generator ROM appears in the CPU address space, and the I/O devices are not accessible. The CPU only needs to access the character generator ROM when downloading the character set from ROM to RAM. CHAREN can be overridden by other control lines in certain memory configurations. CHAREN will have no effect on any memory configuration without I/O devices. RAM will appear from $D000-$DFFF instead.
Expansion Port[edit | edit source]
The bank switching technique in the C64 also handles external ROM in the form of a cartridge plugged into the expansion port and is linked to the PLA by 2 lines: GAME and EXROM. These lines have been designed to allow a cartridge to map one or two 8 kByte banks of ROM into the system easily by wiring the ROM's enable pin to ROMH/ROML lines of the port. Extra logic on the cartridge can be used to implement more complex behaviour such as Freezers though.
- GAME (pin 8) is pulled logically high (set to 1) through internal pull-up resistor RP4. When a cartridge is attached and GAME is pulled logically low (cleared to 0), the interaction with the CPU Control Lines can enable cartridge ROM to be banked in between $8000-$BFFF and/or $E000-$EFFF. GAME can also have the effect of completely banking out all memory between $1000-$7FFF and $A000-$CFFF (Ultimax mode).
- EXROM (pin 9) is pulled logically high (set to 1) through internal pull-up resistor RP4. When a cartridge is attached and EXROM is pulled logically low (cleared to 0), the interaction with the CPU Control Lines can enable cartridge ROM to be banked in between $8000-$BFFF and/or $E000-$EFFF.
Memory Configurations[edit | edit source]
Because there are 5 latch bits (LORAM, HIRAM, CHAREN, GAME, EXROM) that control the memory configurations, there are 25 = 32 possible memory arrangements or modes. However, in reality, there is duplication and so only 14 different modes actually exist. Each mode is a combination of various-sized memory banks (although are multiples of 4 kBytes or 16 pages). Additionally, the banks are pegged to specific addresses and so their location when switched in or out of memory is fixed. Consequently, the 65536 addressable memory locations are essentially divided into 7 uneven Bank Switching Zones where memory banks can be manipulated.
Bank Switching Zones[edit | edit source]
| Hex Address | Dec Address | Page | Size | Contents |
|---|---|---|---|---|
| $0000-$0FFF | 0-4095 | Page 0-15 | 4 kBytes | RAM (which the system requires and must appear in each mode) |
| $1000-$7FFF | 4096-32767 | Page 16-127 | 28 kBytes | RAM or is unmapped |
| $8000-$9FFF | 32768-40959 | Page 128-159 | 8 kBytes | RAM or cartridge ROM |
| $A000-$BFFF | 40960-49151 | Page 160-191 | 8 kBytes | RAM, BASIC interpretor ROM, cartridge ROM or is unmapped |
| $C000-$CFFF | 49152-53247 | Page 192-207 | 4 kBytes | RAM or is unmapped |
| $D000-$DFFF | 53248-57343 | Page 208-223 | 4 kBytes | RAM, Character generator ROM, or I/O registers and Color RAM |
| $E000-$FFFF | 57344-65535 | Page 224-255 | 8 kBytes | RAM, KERNAL ROM or cartridge ROM |
Mode Table[edit | edit source]
This table displays the 32 modes of bank switching.
| Mode | PLA Latch Bit States | Memory Configuration | |||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Expansion Port | CPU Control Lines | Page 0-15 | Page 16-127 | Page 128-159 | Page 160-191 | Page 192-207 | Page 208-223 | Page 224-255 | |||||||||||||
| _EXROM | _GAME | CHAREN | HIRAM | LORAM | $0000-$0FFF | $1000-$7FFF | $8000-$9FFF | $A000-$BFFF | C000-$CFFF | $D000-$DFFF | $E000-$FFFF | ||||||||||
| 31 | 1 | 1 | 1 | 1 | 1 | RAM | RAM | RAM | BASIC ROM | RAM | I/O | KERNAL ROM | |||||||||
| 30 | 1 | 1 | 1 | 1 | 0 | RAM | RAM | RAM | RAM | RAM | I/O | KERNAL ROM | |||||||||
| 29 | 1 | 1 | 1 | 0 | 1 | RAM | RAM | RAM | RAM | RAM | I/O | RAM | |||||||||
| 28 | 1 | 1 | 1 | 0 | 0 | RAM | RAM | RAM | RAM | RAM | RAM | RAM | |||||||||
| 27 | 1 | 1 | 0 | 1 | 1 | RAM | RAM | RAM | BASIC ROM | RAM | CHAR ROM | KERNAL ROM | |||||||||
| 26 | 1 | 1 | 0 | 1 | 0 | RAM | RAM | RAM | RAM | RAM | CHAR ROM | KERNAL ROM | |||||||||
| 25 | 1 | 1 | 0 | 0 | 1 | RAM | RAM | RAM | RAM | RAM | CHAR ROM | RAM | |||||||||
| 24 | 1 | 1 | 0 | 0 | 0 | RAM | RAM | RAM | RAM | RAM | RAM | RAM | |||||||||
| 23 | 1 | 0 | 1 | 1 | 1 | RAM | - | CART ROM LO | - | - | I/O | CART ROM HI | |||||||||
| 22 | 1 | 0 | 1 | 1 | 0 | RAM | - | CART ROM LO | - | - | I/O | CART ROM HI | |||||||||
| 21 | 1 | 0 | 1 | 0 | 1 | RAM | - | CART ROM LO | - | - | I/O | CART ROM HI | |||||||||
| 20 | 1 | 0 | 1 | 0 | 0 | RAM | - | CART ROM LO | - | - | I/O | CART ROM HI | |||||||||
| 19 | 1 | 0 | 0 | 1 | 1 | RAM | - | CART ROM LO | - | - | I/O | CART ROM HI | |||||||||
| 18 | 1 | 0 | 0 | 1 | 0 | RAM | - | CART ROM LO | - | - | I/O | CART ROM HI | |||||||||
| 17 | 1 | 0 | 0 | 0 | 1 | RAM | - | CART ROM LO | - | - | I/O | CART ROM HI | |||||||||
| 16 | 1 | 0 | 0 | 0 | 0 | RAM | - | CART ROM LO | - | - | I/O | CART ROM HI | |||||||||
| 15 | 0 | 1 | 1 | 1 | 1 | RAM | RAM | CART ROM LO | BASIC ROM | RAM | I/O | KERNAL ROM | |||||||||
| 14 | 0 | 1 | 1 | 1 | 0 | RAM | RAM | RAM | RAM | RAM | I/O | KERNAL ROM | |||||||||
| 13 | 0 | 1 | 1 | 0 | 1 | RAM | RAM | RAM | RAM | RAM | I/O | RAM | |||||||||
| 12 | 0 | 1 | 1 | 0 | 0 | RAM | RAM | RAM | RAM | RAM | RAM | RAM | |||||||||
| 11 | 0 | 1 | 0 | 1 | 1 | RAM | RAM | CART ROM LO | BASIC ROM | RAM | CHAR ROM | KERNAL ROM | |||||||||
| 10 | 0 | 1 | 0 | 1 | 0 | RAM | RAM | RAM | RAM | RAM | CHAR ROM | KERNAL ROM | |||||||||
| 9 | 0 | 1 | 0 | 0 | 1 | RAM | RAM | RAM | RAM | RAM | CHAR ROM | RAM | |||||||||
| 8 | 0 | 1 | 0 | 0 | 0 | RAM | RAM | RAM | RAM | RAM | RAM | RAM | |||||||||
| 7 | 0 | 0 | 1 | 1 | 1 | RAM | RAM | CART ROM LO | CART ROM HI | RAM | I/O | KERNAL ROM | |||||||||
| 6 | 0 | 0 | 1 | 1 | 0 | RAM | RAM | RAM | CART ROM HI | RAM | I/O | KERNAL ROM | |||||||||
| 5 | 0 | 0 | 1 | 0 | 1 | RAM | RAM | RAM | RAM | RAM | I/O | RAM | |||||||||
| 4 | 0 | 0 | 1 | 0 | 0 | RAM | RAM | RAM | RAM | RAM | RAM | RAM | |||||||||
| 3 | 0 | 0 | 0 | 1 | 1 | RAM | RAM | CART ROM LO | CART ROM HI | RAM | CHAR ROM | KERNAL ROM | |||||||||
| 2 | 0 | 0 | 0 | 1 | 0 | RAM | RAM | RAM | CART ROM HI | RAM | CHAR ROM | KERNAL ROM | |||||||||
| 1 | 0 | 0 | 0 | 0 | 1 | RAM | RAM | RAM | RAM | RAM | RAM | RAM | |||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | RAM | RAM | RAM | RAM | RAM | RAM | RAM | |||||||||
Mode Table Notes[edit | edit source]
- The default is mode 31 (no cartridge) as all latch bits are logically high (set to 1).
- Modes 16-23 are Ultimax compatibility modes.
- "-" means "open" or "unmapped": No (internal) chip of the C64 is enabled, and the data bus can be written to by the cartridge, just like in the "CART ROM" states.
- "I/O" includes Color RAM as well ($D800-$DBFF)
- $DE00-$DFFF is special and reserved for I/O with chips on the expansion port (by wiring the IOx lines of the port to the enable pins of the chips)
- A cartridge may configure the system to one of the modes 0-23 as one or both of the expansion port latch bits will be logically low (cleared to 0) by grounding the EXROM/GAME lines.
- For cartridges that statically ground EXROM/GAME, manipulation during run-time is limited to the CPU control lines.
- This means that bank switching is confined within a group of modes (within modes 0-7, 8-15, 16-23 or 24-31).
- For example, from mode 31 the system can bank switch to mode 27 but not to mode 12.
- For example, from mode 2 the system can bank switch to mode 7 but not to mode 19.
- For cartridges that include own logic, more complex behaviour can be implemented.
- Modes 16-23 and additional cartridge logic allow arbitrary chips (be it ROMs, RAMs, or even other chips such as additional CIAs) to be visible to the CPU at $1000-$CFFF/$DE00-$FFFF.
Optimised Mode Table[edit | edit source]
Although the results are the same as the Mode Table, this table is condensed for ease of reference.
| Modes | PLA Latch Bit States | Memory Configuration | |||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Expansion Port | CPU Lines | Page 0-15 | Page 16-127 | Page 128-159 | Page 160-191 | Page 192-207 | Page 208-223 | Page 224-255 | |||||||||||||
| EXROM | GAME | CHAREN | HIRAM | LORAM | $0000-$0FFF | $1000-$7FFF | $8000-$9FFF | $A000-$BFFF | C000-$CFFF | $D000-$DFFF | $E000-$FFFF | ||||||||||
| 31 | 1 | 1 | 1 | 1 | 1 | RAM | RAM | RAM | BASIC ROM | RAM | I/O | KERNAL ROM | |||||||||
| 30, 14 | X | 1 | 1 | 1 | 0 | RAM | RAM | RAM | RAM | RAM | I/O | KERNAL ROM | |||||||||
| 29, 13 | X | 1 | 1 | 0 | 1 | RAM | RAM | RAM | RAM | RAM | I/O | RAM | |||||||||
| 28, 24 | 1 | 1 | X | 0 | 0 | RAM | RAM | RAM | RAM | RAM | RAM | RAM | |||||||||
| 27 | 1 | 1 | 0 | 1 | 1 | RAM | RAM | RAM | BASIC ROM | RAM | CHAR ROM | KERNAL ROM | |||||||||
| 26, 10 | X | 1 | 0 | 1 | 0 | RAM | RAM | RAM | RAM | RAM | CHAR ROM | KERNAL ROM | |||||||||
| 25, 9 | X | 1 | 0 | 0 | 1 | RAM | RAM | RAM | RAM | RAM | CHAR ROM | RAM | |||||||||
| 23, 22, 21, 20, 19, 18, 17, 16 | 1 | 0 | X | X | X | RAM | - | CART ROM LO | - | - | I/O | CART ROM HI | |||||||||
| 15 | 0 | 1 | 1 | 1 | 1 | RAM | RAM | CART ROM LO | BASIC ROM | RAM | I/O | KERNAL | |||||||||
| 12, 8, 4, 0 | 0 | X | X | 0 | 0 | RAM | RAM | RAM | RAM | RAM | RAM | RAM | |||||||||
| 11 | 0 | 1 | 0 | 1 | 1 | RAM | RAM | CART ROM LO | BASIC ROM | RAM | CHAR ROM | KERNAL ROM | |||||||||
| 7 | 0 | 0 | 1 | 1 | 1 | RAM | RAM | CART ROM LO | CART ROM HI | RAM | I/O | KERNAL ROM | |||||||||
| 6 | 0 | 0 | 1 | 1 | 0 | RAM | RAM | RAM | CART ROM HI | RAM | I/O | KERNAL ROM | |||||||||
| 5 | 0 | 0 | 1 | 0 | 1 | RAM | RAM | RAM | RAM | RAM | I/O | RAM | |||||||||
| 3 | 0 | 0 | 0 | 1 | 1 | RAM | RAM | CART ROM LO | CART ROM HI | RAM | CHAR ROM | KERNAL ROM | |||||||||
| 2 | 0 | 0 | 0 | 1 | 0 | RAM | RAM | RAM | CART ROM HI | RAM | CHAR ROM | KERNAL ROM | |||||||||
| 1 | 0 | 0 | 0 | 0 | 1 | RAM | RAM | RAM | RAM | RAM | RAM | RAM | |||||||||
Optimised Mode Table Notes[edit | edit source]
- Although there are 17 lines in the table, there remain 14 different modes.
- The "X" state of the latch bit is irrelevant, as the mode will be chosen regardless of being logically high (set to 1) or low (cleared to 0).
- All Mode Table Notes remain valid.
Links[edit | edit source]
FIXME: Include info from The Transactor Volume 6, Issue 05, page 55 - R(BA) vs. R(~BA); what memory does the VIC see? This will be added to the VIC page shortly.
